PCB Design for ESP32 Stand alone module
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@Sharmila GPIO0 must not be low all the time. It must be held low only for a moment. Because GPIO0 is a boot strap option for choosing between UART download and normal operation. Please refer to the datasheet and search boot strap. And also can you please post a snap of your newly designed board please?
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@kowshik1729 thank you for the hint ! i will check it . schematic picture of my board is given below
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@kowshik1729 sorry, gpio 0 is low only till it is programmed. after that this will disconnected.
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@Sharmila Reviewed your schematics. Have the following doubts
- Is this a USB receptacle?
- Didn't find any option where you can pull the GPIO0 low and bring it back to normal state. Did you have a jumper connection or button between GPIO0 and GND?
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- no.
- we are using jumper for gpio 0th pin. please refer the below image.
Recent Posts
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Hi all,
I recently came across this post where they have shown photos printed on PCB in high resolution. I would like to know how to add this kind of photos to the silkscreen layers of the PCB in Eagle/Altium.
Adding such kind of photos will be attractive for beginners and also can be used for educational purposes too.
Please let me know in case anybody knows. -
@kowshik1729 I think that might not get since the platform is not opensource! but they provided everything you need to develop a system with that.
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@kowshik1729 Carrier board schematics for SoMs will be always available as they need to be modified as per customer application, however SoM design files are hard to get unless the H/W design is truly open-source.
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@salmanfaris Actually the schematics files you've mentioned are the same files which I've got from them. They are carrier board design files.
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@kowshik1729 Please check this, it might help you,
Jetson Nano Module Datasheet Jetson Nano Product Design Guide Jetson Nano Thermal Design Guide Jetson Nano 3D CAD STEP Model Jetson Nano Developer Kit 3D CAD STEP Model Jetson Nano Pinmux Table Jetson Nano Developer Kit Pinmux Table Jetson Nano Reference Design Schematics More resourceoriginally drafted and shared by dusty_nv